Friday, September 3, 1993

For the record:		TA's office hours are 3-5 on TuTh
---
ASSIGNMENT: read chapter 4
---
Today's topics (from Chapter 2):	CPU/Device interface; Interrupts
-------------------------------------------------------------------------------
CPU/Device interface

Assume von Neumann architecture.  Each device has a small hardware
buffer (one record).

"Handshaking" - CPU responsible for data transfer.  Device raises flag
when in consistent state (information all in or out).  CPU copies
information and tells device to perform next operation.

CPU control:  Busy waiting
	repeat {
		while(device busy) {};
		transfer record;
		notify device;
	} until(transfer finished)
Pro: easy to implement.  requires little extra hardware
Con: least efficient in terms of resource use.  CPU blocked (idle, not
working).  Note order of magnitude differences (or greater) in speed

CPU control: Polling
	CPU loads appropriate registers and initiates operation
	CPU finds something else to do
	From time to time CPU queries hardware flag to see if device
	finished.  If so, CPU performs appropriate action; If not, CPU
	continues on with other task
Pro: Concurrent CPU use can be more efficient
Con: Timing considerations.  Poll too often, inefficient for CPU.
     Poll too infrequently, device idle or possibly input lost

Asynchronous control: Interrupts
	CPU loads appropriate registers and intiates operation
	CPU carries on with another task
	When device completes data transfer it informs CPU with interrupt
	CPU stops what is is doing and transfers control to interrupt
		handler (located at predefined location in memory)
Pro: concurrent operation
But: what if more than one device or if additional interrupts occur
	while first is being serviced?

What are interrupts used for?	[also called "traps"]
	External events: i/o, timers)
	Internal events: system calls, errors (illegal instruction,
		addressing violation, operand out of range, etc.),
		page faults, etc.

Implementation of interrupts
	- multiple classes of interrupts, perhaps each generated by
	  one of several different events
	- *interrupt handler* --- small software routine that determines
	  what caused interrupt and what to do about it (e.g., action
	  on i/o is to transfer information) [also called interrupt
	  service routine]
	- reserved set of locations in low memory that are always
	  resident provide indices to interrupt handlers [vector]
Hardware instruction cycle becomes:
	while (true)  {
		fetch next instruction
		increment instruction counter
		carry out instruction
		if interrupt pending then  {
			store instruction counter, save state as necessary
			jump to the appropriate handler by setting
				the instruction counter to the
				handler's address (from the vector)
		}
	}
Handler executes then restores previous state if appropriate (when not?)

Where is return address stored?	Fixed location/handler location/sys stack
How many interrupts can be active at a given time?
	One: disable interrupts during handling.  if not, new
		overwrites old's  data: lost interrupt
	Many: priority system to decide which to handle and to enable
		masking (higher masks same and lower) [selectively disables],
		permits higher priority interrupts
	Alternately can define system without such strong hierarchy (e.g.,
		block specific classes of interrupts as in Unix)
	What happens to pending interrupts:  in Unix only the last at
		a level is remembered.
	Hence interrupt handler has to be quick (e.g., transfer
		character and then return rather than trying to	process)

What if interrupts arrive too quickly---swamp CPU or worse, lost
because interrupt handler can't keep up?

Decrease amount of CPU processing needed by increasing amount of data moved
-------------------------------------------------------------------------------
Direct Memory Access (DMA)
	high speed I/O devices
	device transfers block of data to memory directly with no
		intervention by CPU (e.g., around 128 to 4096 bytes)
	device notifies CPU that data has been transfered
Extension: *channels*---special purpose processors that also offload
some of CPU's work in handling device errors, code conversion and
formatting functions during DMA process
-------------------------------------------------------------------------------
Other examples of interrupts

Timers
- make sure that OS regains control from time to time to insure
  that a runaway process can be checked
- also used to implement time sharing to define time-slices
- time of day clock, etc.

User-generated signals to processes:  e.g., Unix SIGHUP, SIGQUIT, SIGKILL

Consider Dual-Mode instructions: user mode and monitor mode (monitor
mode also called system mode or supervisor mode)
	mode-bit in hardware specifies mode
	some instructions limited to use in supervisor mode---behave
		differently in user mode or NOP (e.g., "halt")

Implement hardware protection
	for example memory (interrupt vectors, OS data structures, etc.)
	- base and limit registers specify range of legal user addresses
	- hardware insures that all user address references are in
	  legal range.  Trap results if not
	- base and limit registers set by monitor mode instruction
	  hence user routines cannot change limits